1. Field of the Invention
The present invention relates to semiconductor integrate circuits and memory processing systems, and more particularly to structures for high-speed data transfer.
2. Description of the Background Art
Double data rate synchronous dynamic random access memories (hereinafter referred to as DDR-SDRAMS) employ SSTL2 (SSTL: Stub Series Terminated Transceiver Logic), which is standardized by JEDEC (Joint Electron Device Engineering Council), as an interface for data transfer.
SSTL2 is based on termination. SSTL2 has two types of data transfer scheme: in one data transfer scheme, a transmission line is terminated only at one end (SSTL2 class 1) and in another, a transmission line is terminated at both ends (SSTL2 class 2). In conventional DDR-SDRAMs, SSTL2 class 2 has been employed where the transmission line is terminated at both ends.
With the conventional data transfer scheme, however, a problem rises at the implementation in a server. A first problem in the conventional DDR-SDRAM will be described with reference to FIG. 18. FIG. 18 shows the relation between memory modules 900A, 900B and 900C and a system controller 902 transmitting/receiving signals to/from the memory modules. The memory modules and system controller 902 are mounted on a main board not shown.
DDR-SDRAM is mounted on a module substrate constituting the memory module. Each DDR-SDRAM is responsive to a control signal sent from system controller 902 to supply stored data to system controller 902 as an output. The data is transferred to system controller 902 via data transmission lines 90a, 90b, . . . , 90m. In addition, the memory module receives data from system controller 902 via data transmission lines 90axcx9c90m and stores the data. System controller 902 and memory modules receive an external clock signal EXTCLK determining an operation timing from a clock generator not shown.
Data transmission lines 90axcx9c90m, being SSTL2 class 2 described above, are terminated at both ends, that is, at the side of system controller 902 and at the side opposite to system controller 902. As an example of a termination technique, a case where resistance elements R1 and R2 are employed will be described. Resistance elements R1 and R2 are connected between a node receiving a power supply voltage Vtt and an end of the data transmission line.
As shown in the figure, when the data transmission lines are gathered around system controller 902, the area around system controller 902 becomes excessively congested with the termination elements of the data transmission lines. Here, as the amount of data to be processed increases, the implementation becomes more difficult.
A second problem in the conventional DDR-SDRAM will be described with reference to FIG. 19. FIG. 19 shows the relation between a memory chip and an impedance in a data transmission line 90. Memory modules are electrically connected to data transmission line 90 at nodes ne, nf, ng, . . . , respectively. In FIG. 19, a memory chip 910 included in memory module 900A is shown as a representative.
Memory chip 910 includes a DLL (delayed locked loop) circuit 920 generating an internal clock signal for determining the timing of internal operations according to an external clock signal, a data output buffer 930 for externally supplying data as an output and a data input buffer 940 for taking in data received from system controller 920. Symbol CLK represents a clock pin taking in the external clock signal and DQS represents a pin corresponding to a data strobe signal determining the timing of input/output of data.
Here, let Z0 represent a characteristic impedance of a data transmission line (between system controller 902 and node ne) as a reference, L0 a characteristic inductance, and C0 a characteristic capacitance. Impedance Z0 can be represented by the expression (1). Assume that the input capacitance is Cin and the memory module is implemented with a predetermined pitch Pitch, the impedance at node
nf lowers from Z0 to Z1. Impedance Z1 is represented by the expression (2).                     Z0        =                              L0            C0                                              (        1        )                                Z1        =                              L0                          C0              +                              Cin                Pitch                                                                        (        2        )            
Thus the particular problem exists at the time of implementation that the impedance changes with the arrangement of memory chips memory modules). This effect is more apparent in a commonly-employed memory expansion technique where the memory is expanded later.
With reference to FIG. 20, an example where module substrates are mounted at different positions on the main board from each other will be described. In an A type mounting, for example, data arrives at system controller 902 in approximately the same phase with external clock signal EXTCLK (at time t1). On the other hand, in a B type mounting, data arrival at system controller 902 (at time t2) lags the external clock signal EXTCLK. Further, in a C type mounting, data arrives system controller 902 (at time t0) earlier than external clock signal EXTCLK and data receipt completes (at time t3) earliest among three exemplary types of mounting. Thus, the difference in the timing of data arrival stems from the change in impedance depending on the type of mounting.
Now, to accommodate the memory expansion in the future, a set up time of system controller 902 is set to (t2xcx9ctx) and a hold time is set to (txxcx9ct3) (here, t2 less than tx less than t3). This setting allows the device to be applied to any types of mounting of memories.
When the set up time/hold time are to be set such that they are applicable to any types of mounting, the set up time and hold time inevitably becomes short. In an actual 133 MHz DDR-SDRAM, the set up time/hold time is too short, and together amounts only 1000xc3x9710xe2x88x9212 seconds (1000 pico seconds).
As can be seen from the above, it has been difficult to secure sufficient set up time/hold time which are important parameters for data transfer in the structure of the conventional memory processing system.
Thus, the present invention provides a memory processing system capable of securing sufficient set up time/hold time allowing the memory expansion and the high-speed processing.
A memory processing system according to one aspect of the present invention includes: a plurality of memory chips; a system controller controlling each of the plurality of memory chips; and a data transmission line for transferring data between the system controller and the plurality of memory chips; each of the plurality of memory chips including a test circuit responsive to a request from the system controller to perform a test for measuring data transmission distance of the data transmission line to the system controller, the system controller determining for each of the plurality of memory chips a set up time/hold time for receiving the data based on the measurement result at the test circuit.
According to the memory processing system described above, the set up time/hold time can be determined independently for each memory chip. Then, the ratio of set up time/hold time becomes larger in the memory processing system according to the present invention than in the conventional system. In other words, the set up time/hold time, which serves as an important parameter for data transfer, can be sufficiently secured. Therefore, high-speed data transfer can be achieved regardless of the type of mounting and subsequent memory expansion.
Preferably in. the memory processing system, termination is made only at one end opposite to the side of the system controller. Hence, the line length can be made equal in compliance with JEDEC standard through line folding and so on utilizing the region at the side of the system controller where the termination elements have conventionally been arranged.
Preferably, the memory processing system monitors the reflected wave of an output signal. Then, the length of the data transmission line can be measured based on the change in potential of the data transmission line.
Particularly, the memory processing system includes: a clock generator supplying an external clock signal determining an operation timing to the system controller and the plurality of memory chips; a first clock line for supplying the external clock signal to the system controller from the clock generator; and a second clock line of substantially equal length with the first clock line for supplying the external clock signal to each of the plurality of memory chips from the clock generator; wherein the monitor register includes a plurality of registers taking in a signal received at the pin at first predetermined intervals in response to a first pulse train generated based on the external clock signal, the system controller includes, a trace register recording a value of the monitor register in each of the plurality of memory chips, a plurality of input buffers taking in data on the data transmission line at second predetermined intervals in response to a second pulse train generated based on the external clock signal, and a select circuit selecting data taken in at one of input buffers among the plurality of input buffers according to a value recorded in the trace register for each of the plurality of memory chips.
Particularly, the test is performed periodically at a predetermine cycle, and each value of the plurality of registers and a value of the trace register are updated every time the test is performed.
According to the memory processing system as described above, the system controller can adjust the set up time/hold time at predetermined intervals based on the result of monitoring of the reflected wave of the output signal.
In addition, through a regular test operation and an update of register value, drift in temperature and voltage lasting for a long time can be followed and further stability is guaranteed.
Further, the present invention provide a semiconductor integrated circuit capable of high-speed data transfer with an external source.
A semiconductor integrated circuit according to another aspect of the present invention includes: a memory cell array including a plurality of memory cells; a read circuit for reading data from the memory cell array; a write circuit for writing data into the memory cell array; a data input/output pin for receiving data to be written into the memory cell array from an external source/transmitting data read out from the memory cell array to an external source; and a test circuit for measuring data transmission distance to the external source.
Preferably, the test circuit includes, an output circuit supplying a test signal from the data input/output pin, and a monitor register electrically connected to the data input/output pin to monitor the change in potential of the data input/output pin.
Particularly, a data transmission line is connected between the data input/output pin and the external source transmitting data to be written into the memory cell array and receiving data read out from the memory cell array, the data transmission line is connected to the external source at one end and terminated only at another end.
According to the semiconductor integrated circuit described above, data transmission distance to the external source can be measured. Thus, the side receiving data from the semiconductor integrated circuit according to the present invention can appropriately adjust the set up time/hold time. Therefore, when the memory module is configured with the semiconductor integrated circuit according to the present invention, high-speed data transfer will be allowed regardless of the type of mounting and subsequent memory expansion.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.